Conference Coverage
ESL – where we’re at and where we’re going
By Bill Murray
03/09/10
Gary Smith of GarySmithEDA presented an ESL snapshot at the recent OSCI SystemC day at DVCon 2010. He talked about the progress of ESL, its five high value applications, market sizing, and concluded with some comments about its ability to satisfy the needs of the embedded system software developer.
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News Analysis
Consortium to develop smart local grid management SoC/SiP and infrastructure concept
By Bill Murray
03/08/10
The energy saving benefits of the smart power supply grid are well documented. But what about the savings potential of smart local energy grids? The SmartCoDe project aims to use ESL design techniques to devise an SoC/SiP design and operating infrastructure concept that enables energy monitoring and control at the home appliance level – and at a price that consumers can afford. We ask Christoph Grimm and Peter Neumann how.
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First Look
X-Fab first pure play foundry to deliver single-block embedded NVRAM
By Bill Murray
03/04/10
First, X-Fab integrated optoelectronics into its 350nm analog mixed signal process. Now, it has enhanced its 180nm modular, mixed signal high voltage CMOS process with embedded non-volatile RAM. The offering combines the fast access of SRAM with the data retention of EEPROM and Flash – and eliminates an external memory chip. We dig below the press release in an interview with product marketing manager, Olaf Zinke.
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News Analysis
Semico projects double-digit revenue growth for semiconductor market
By Bill Murray
03/02/10
Semico Research’s president, Jim Feldhan, projects semiconductor revenues to grow 24 percent from 2009 to 2010, and another 11.5 percent from 2010 to 2011. His analysis looks at the drivers and evaluates their effect on production, and concludes that the “good times are here!”
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Contributed Article
Overcoming multicore architecture complexities in networking equipment
By Eric Carmès
02/17/10
6Wind’s CEO describes the conditions that new software architectures must meet to provide an efficient and transparent solution for a fast migration to multicore. He lays out the system challenge; discusses network equipment architecture, considers possible implementations for multicore packet processing, and concludes with a list of requirements for a successful migration.
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Contributed Article
Static verification - what’s old is new again
By Ping Yeung
02/17/10
Mentor engineer Ping Yeung reviews the spectrum of static verification methodologies from RTL Lint checking, through static checks, formal checks, automated formal applications, to formal property checking. He hammers home the point that static verification finds bugs that simulation often misses – and earlier in the design cycle. Yeung argues that it’s time to give static verification methodologies another look.
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In My Opinion
Is HLS finally converging on a standard language?
By Brett Cline
02/16/10
Is a new language war brewing? Or is high level synthesis (HLS) finally converging on a standard language, SystemC? Forte’s Brett Cline argues the latter case and explains why.
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Contributed Article
Using formal verification for SoC integration
By Antonio Dimalanta and Sebastian Skalberg
02/11/10
How do you verify SoC integration? How do you catch the myriad bugs that can occur in chip level connectivity, the pad-ring, the registers, and multi-cycle paths? Jasper’s Antonio Dimalanta and Sebastian Skalberg describe how – and how to slash verification time and effort by 33% to 75%.
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First Look
Sigrity launches thermal/electrical co-simulation environment
By Bill Murray
01/28/10
According to Sigrity, its new PowerDC Thermal tool is the first to support the automatic co-simulation of thermal and electrical behavior, eliminating the iterative, manual simulate-and-analyze process necessitated by the traditional dual-simulator approach. The new tool operates at the board and package level, and comprehends chip data, too.
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In My Opinion
Waving goodbye to phantom DRC errors
By Michael White
01/27/10
When migrating IP to new process nodes or different foundries, previously-waived DRC errors can create phantom DRC errors. Such phantoms can cost just as much time and effort to debug as real errors. Mentor’s Michael White posits an effective solution.
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